| System Features |
| 1. |
1.5KW OTP program memory |
| 2. |
128 Bytes data RAM |
| 3. |
Maximum 6 IO pins can be selected as TOUCH PAD individually, each featuring noise immunity |
| 4. |
One hardware 16-bit timer |
| 5. |
Two hardware 8-bit timers with PWM generation (Timer2/Timer3), Timer2/Timer3 also configured with NILRC oscillator. |
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Its frequency is slower than ILRC and suitable for a more power-saving wake-up clock |
| 6. |
One set triple 11bit SuLED (Super LED) PWM generators and timers (LPWMG0/LPWMG1/LPWMG2) |
| 7. |
One hardware comparator |
| 8. |
6 IO pins with optional pull-high/pull-low resistor |
| 9. |
Bandgap circuit to provide 1.2V Bandgap voltage |
| 10. |
Clock sources: internal high RC oscillator and internal low RC oscillator |
| 11. |
14 Levels of LVR reset: 4.5V, 4.0V, 3.75V, 3.5V, 3.3V, 3.15V, 3.0V, 2.7V, 2.5V, 2.4V, 2.3V, 2.2V, 2.1V, 2.0V |
| 12. |
Two selectable external interrupt pins |
| 13. |
Internal LDO to prevent touch noise |
| 14. |
Support low-power wake-up ‘stopsys’ by NILRC |
| 15. |
IOH: 18 mA , IOL: 25 mA |
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| CPU Features |
| 1. |
Operating modes: One processing unit mode |
| 2. |
82 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer to provide adjustable stack level (Using 2 bytes SRAM for one stack level) |
| 5. |
Direct and indirect addressing modes for data and instructions |
| 6. |
All data memories are available for use as an index pointer |
| 7. |
Separated IO and memory space |
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