| System Features |
| 1. |
2KW OTP program memory |
| 2. |
128 Bytes data SRAM |
| 3. |
One hardware 16-bit timer |
| 4. |
Two hardware 8-bit timers with PWM generator |
| 5. |
One hardware comparator |
| 6. |
Band-gap circuit to provide 1.20V reference voltage |
| 7. |
Up to 12-channel 12-bit resolution R-Type ADC |
| 8. |
Max. 14 IO pins with optional pull-high / pull-low resistor |
| 9. |
Every IO pin can be configured to enable wake-up function |
| 10. |
Clock sources: IHRC, ILRC & EOSC (XTAL) |
| 11. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
| 12. |
8 selectable levels of LVR reset from 1.8V to 4.5V |
| 13. |
Two selectable external interrupt pins by code option |
| 14. |
Built-in half VDD bias voltage generator to provide maximum 5x9 dots LCD display |
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| CPU Features |
| 1. |
8-bit high performance RISC CPU |
| 2. |
86 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer and adjustable stack level |
| 5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
| 6. |
IO space and memory space are independent |
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