◆◆ PFC460 ◆◆
High EFT series
Fit for AC powered with even using RC step-down circuit, or required high EFT capability (±4KV) for passing safety regulation tests, ESD > 8 KV.
Operating temperature range: -40°C ~ 85°C
System Features
1. 4KW MTP program memory for four FPPA units (programming cycle at least 1,000 times)
2. 512 Bytes data SRAM for four FPPA units
3. One hardware 16-bit timer
4. Two hardware 8-bit timers with PWM generation (Timer2/Timer3), Timer2/Timer3 also c
5. Timer2/Timer3 PWM resolution is 6/7/8 bit
6. Three hardware 11-bit PWM generators (PWMG0/PWMG1/PWMG2)
7. One set triple 11bit SuLED (Super LED) PWM generators and timers(LPWMG0/LPWMG1/LP
8. Provide one PFG hardware circuit for precise frequency output
9. Provide one hardware comparator
10. Provide one OP Amplifier (OPA)
11. Provide 1T 8x8 hardware multiplier
12. 26 IO pins with optional pull-high / pull-low resistor
13. Every IO pin can be configured to enable wake-up function
14. For every wake-up enabled IO, two optional wake-up speed are supported: normal an
15. Up to 24 IO pins could be selected as touch keys
16. Bandgap circuit to provide 1.20V reference voltage
17. Up to 28-channel 12-bit resolution ADC with one channel comes from internal Bandgap
18. Provide ADC reference high voltage: external input, internal VDD, Bandgap(1.20V),
19. Clock sources: internal high RC oscillator (IHRC), internal low RC oscillator (ILRC
20. Provide four IO output capabilities to satisfy different application requirements
  (1) PB0 drive current could option 0/10mA, and it sink current could option 108/20mA
  (2) PB2~PB7 drive current could option 28/10mA, and it sink current could option 75/2
  (3) PA0~PA4 drive/sink current =10mA/20mA
  (4) PA5~PA7, PB1, PC0~PC7, PD0~PD1 drive/sink current =10mA/14mA
21. Built-in VDD/2 bias voltage generator to provide 5COM×21SEG dots LCD display
22. 14 selectable levels of LVR reset from 2.0V to 4.5V
23. selectable external interrupt pins
CPU Features
1. Operating modes: Four processing units FPPATM mode or Traditional one processing unit mode
2. 104 powerful instructions
3. Most instructions are 1T execution cycle
4. Programmable stack pointer and adjustable stack level
5. Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode
6. Register space, SRAM memory space and MTP space are independent
Content Date Version Download
PFC460 datasheet 2023-12-27 released v0.04 Download(CN): Download(EN):
Package Information 2023-09-13 released v0.14 Download(CN): Download(EN):
CS Testing 2022-07-06 released Download(CN): Download(EN):
Content Date Version Download
IDE software 2024-06-12 released v1.01A3 Download(EN):
Program Writer software 2024-06-12 released v1.01A3 Download(EN):
Touch Library 2021-12-17 released v1.7 Download(CN):
Content Description Download
APN001 Output impedance of ADC analog signal source Download(CN): Download(EN):
APN002 Over voltage protection Download(CN): Download(EN):
APN003 Over voltage protection Download(CN): Download(EN):
APN004 Semi-Automatic writing handler Download(CN): Download(EN):
APN005 Effects of over voltage input to ADC Download(CN): Download(EN):
APN007 Setting up LVR level Download(CN): Download(EN):
APN011 Semi-Automatic writing Handler improve writing stability Download(CN): Download(EN):
APN013 Notification of crystal oscillator Download(CN): Download(EN):
APN015 Capacitive touch screen PCB design guide Download(CN): Download(EN):
APN017 Improve IC anti-interference ability under power plug test Download(CN): Download(EN):
APN019 E-PAD PCB layout guideline Download(CN): Download(EN):