| System Features |
| 1. |
2KW MTP program memory for both FPP units (programming cycle at least 1,000 times) |
| 2. |
128 Bytes data RAM for both FPP units |
| 3. |
One hardware 16-bit timer |
| 4. |
Two hardware 8-bit timer with PWM generator |
| 5. |
Three hardware 11-bit PWM generators (PWMG0, PWMG1 & PWMG2) |
| 6. |
Provide one hardware comparator |
| 7. |
Provide one OP Amplifier (OPA) |
| 8. |
Provide 1T 8x8 hardware multiplier |
| 9. |
14 IO pins and optional pull-high resistor |
| 10. |
Every IO pin can be configured to enable wake-up function |
| 11. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
| 12. |
Bandgap circuit to provide 1.20V reference voltage |
| 13. |
Up to 12-channel 12-bit resolution ADC with one channel comes from internal Bandgap reference voltage or 0.25*VDD |
| 14. |
Provide ADC reference high voltage: external input, internal VDD, Bandgap(1.20V), 4V, 3V, 2V |
| 15. |
Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator |
| 16. |
Built-in VDD/2 bias voltage generator to provide maximum 5×9 dots LCD display |
| 17. |
8 selectable levels of LVR reset from 1.8V to 4.5V |
| 18. |
Four selectable external interrupt pins |
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