| System Features |
| 1. |
4KW OTP program memory |
| 2. |
256 Bytes data SRAM |
| 3. |
One hardware 16-bit timer |
| 4. |
Two hardware 8-bit timers with PWM generation |
| 5. |
Three hardware 11-bit PWM generators (PWMG0, PWMG1 & PWMG2) |
| 6. |
One hardware comparator |
| 7. |
Bandgap circuit to provide 1.2V reference voltage |
| 8. |
Up to 14-channel 12-bit resolution ADC with one channel comes from internal bandgap |
| 9. |
ADC reference high voltage: external input, internal VDD, Bandgap 1.20V, 4V, 3V, 2V |
| 10. |
One 1T 8x8 hardware multiplier |
| 11. |
Max. 22 IO pins with optional pull-high resistor |
| 12. |
Three different IO Driving capability group to meet different application requireme |
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● PB4, PB7 Drive/ Sink Current= 30mA/35mA (Strong) and 13mA/17mA (Normal) |
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● Other IOs (except PA5) Drive/ Sink Current = 10mA/(13 or 20) mA |
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● PA5 Sink Current = 10mA |
| 13. |
Every IO pin can be configured to enable wake-up function |
| 14. |
Built-in 1/2 VDD LCD bias voltage generator to provide maximum 4x17 dots LCD display |
| 15. |
Clock sources: IHRC, ILRC and EOSC (XTAL) |
| 16. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and |
| 17. |
Eight levels of LVR reset: 4.0V, 3.5V, 3.0V, 2.7V, 2.5V, 2.2V, 2.0V, 1.8V |
| 18. |
Two selectable external interrupt pins by code option |
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| CPU Features |
| 1. |
8bit high performance RISC CPU |
| 2. |
93 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer to provide adjustable stack level |
| 5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
| 6. |
IO space and memory space are independent |
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