| System Features |
| 1. |
On-Chip Memory： |
| |
● FLASH: 32KB MAIN program memory + 8KB NVR data/parameter storage |
| |
● SRAM: 4KB data memory |
| 2. |
Clock Sources： |
| |
● Internal 60MHz high-speed RC oscillator (HIRC), supporting specific integer frequency division |
| |
● Internal 32KHz low-speed RC oscillator (LIRC) |
| 3. |
Multi-Function Timers： |
| |
● 2 x 16-bit basic timers (TIM0/TIM1) |
| |
● 1 x 16-bit low power timer (LPTIM), supporting operation in deep sleep mode |
| |
● 1 x 20-bit advanced timer (TIM2), supporting 4-channel PWM output |
| |
● 1 x 20-bit advanced timer (EPWM), supporting 6-channel (3 complementary pairs) PWM output with programmable dead-time generator and brake protection |
| 4. |
Analog Peripherals： |
| |
● 2 x 8-bit DACs |
| |
● 2 x Comparators (COMP), supporting hysteresis voltage and EPWM brake triggering |
| |
● 2 x Programmable gain amplifiers (PGA) with selectable gain from 1× to 16× |
| |
● 1 x 12-bit SAR ADC, up to 1Msps sampling rate, with 16 channels (including internal thermal sensor, reference voltage, and PGA outputs) |
| 5. |
Communication Interfaces： |
| |
● 1 x UART, up to 115.2Kbps, supporting various data formats and hardware error detection |
| |
● 1 x SPI, max master speed 15Mbps, max slave speed 7.5Mbps |
| |
● 1 x I2C, supporting speeds up to 1Mbps |
| 6. |
Hardware Acceleration & Safety： |
| |
● DSP hardware accelerator (32-bit divider, 32-bit square root) |
| |
● Hardware CRC-16/32 calculation unit |
| |
● Watchdog timer (WDG) |
| 7. |
Power Management & Low Power： |
| |
● Operating voltage: 2.5V ~ 5.5V |
| |
● Low power modes: sleep and deep sleep |
| |
● LVR (low voltage reset) threshold: 2.0V ~ 3.7V |
| |
● LVD (low voltage detection) threshold: 2.0V ~ 4.3V |
| 8. |
GPIO & Wake-Up： |
| |
● 22 x GPIO pins, all supporting external interrupts and peripheral multiplexing |
| |
● Supports wake-up from deep sleep via all GPIOs, WDG, or LPTIM (LIRC remains active) |
| 9. |
Identification： |
| |
● Unique 12-byte (96-bit) UID per chip |
| 10. |
Environment & Packaging： |
| |
● Operating temperature: -40°C ~ +85°C |
| |
● Available in SSOP24 or QFN24 (4×4×0.75mm) packages |
| |
|
| CPU Features |
| 1. |
Core Architecture: 32-bit RISC-V CPU core (supporting RV32E/M/C instruction sets) |
| 2. |
Register Resources: 16 x 32-bit general-purpose registers |
| 3. |
Execution Efficiency: Highly efficient 2-stage execution pipeline |
| 4. |
Arithmetic Capabilities： |
| |
● Built-in single-cycle 32 × 32-bit hardware multiplier |
| |
● uilt-in 17-cycle 32-bit hardware divider |
| 5. |
Interrupt Control: Enhanced core local interrupt controller (ECLIC), supporting 2 internal and 15 external interrupts with dynamic priority and nesting |
| 6. |
Timer Resources: Built-in 64-bit system timer |
| 7. |
Debug Interface: Supports 2-wire cJTAG and standard 4-wire JTAG debugging interfaces |
| |
|