| System Features |
| 1. |
1.5KW OTP program memory |
| 2. |
96 Bytes data RAM |
| 3. |
One hardware 16-bit timer |
| 4. |
One hardware 8-bit timers with 6/7/8-bit PWM generation |
| 5. |
5 IO pins with optional pull-high and pull-low resistor (PA0, PA3, PA5, PB0, PB1) |
| 6. |
Three different IO Driving capability group to meet different application requirements |
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(1) PA4, PA6 Drive/ Sink Current= 0.33mA / 0.37mA |
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(2) Other IOs (except PA7) Drive/ Sink Current = 16mA / 18mA |
| 7. |
Every IO pin (except PA4 & PA6) can be configured to enable wake-up function |
| 8. |
Clock sources: IHRC, ILRC & NILRC |
| 9. |
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast |
| 10. |
16 levels of LVR: |
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4.5V, 4.0V, 3.75V, 3.5V, 3.3V, 3.15V, 3.0V, 2.7V, 2.5V, 2.4V, 2.3V, 2.2V, 2.1V, 2.0V, 1.9V, and 1.8V |
| 11. |
One external interrupt pins: PA0 |
| 12. |
Bandgap circuit to provide 1.20V reference voltage |
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| CPU Features |
| 1. |
One processing unit operating mode |
| 2. |
95 powerful instructions |
| 3. |
Most instructions are 1T execution cycle |
| 4. |
Programmable stack pointer to provide adjustable stack level |
| 5. |
Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode |
| 6. |
IO space and memory space are independent |
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